Dual-Buck Three-Switch Leg Converters with Reduced Number of Passive Components

-Like conventional two-switch leg converters, the three-switch leg converters also have short-circuit risks and dangerous shoot-through current is generated if switches of the same leg are turned-on simultaneously. In this article, a new dual-buck structure is proposed for three-switch leg converters. The proposed structure is reliable because of no shoot-through concerns and high quality of output waveforms can be obtained due to the reduction in pulsewidth modulation (PWM) dead-time. Unlike the conventional dual-buck three-switch leg which uses many passive components such as four current limiting inductors and three external diodes, the new dual-buck three-switch leg uses only one current limiting inductor with two external diodes. To verify the performance, the proposed three-switch legs are used in single-phase dual-output inverter and detailed theoretical analysis, simulation, and experiments are performed. Both continuous and discontinuous modulation schemes are applied and it has been figured out that discontinuous modulation scheme can improve the dc-link voltage utilization in the common-frequency mode of operation.


I. INTRODUCTION
Power converters can be categorized into voltage-source converter (VSC) and current-source converter (CSC).The building block of both VSCs and CSCs is generally a switching leg with two active switches.The structures of state-of-the-art two-switch legs (2SL) are shown in Figs.1(a) and (c).The switching leg of Fig. 1(a) has unidirectional voltage blocking capability and is extensively used in dc-ac [see Fig. 1(b)], acdc, and dc-dc VSCs.On the other hand, the switching leg of Fig. 1(c) has bidirectional voltage blocking capability and therefore used in dc-ac [see Fig. 1(d)] and ac-dc CSCs.In spite of some inherent advantages of CSCs, the technology nowadays still prefers to use VSCs due to their advanced researches, better control, and good efficiency [1].
Besides the 2SL, the three-switch leg (3SL) has also gained significant popularity.The reason of getting recognition from scientific community is the capability of 3SL to reduce the number of active switches in various applications and power conversion topologies [2].The active switches require gatedriver circuitry, gate-driver supply, and pulse width modulation (PWM) outputs in microcontroller which undesirably increase the cost, weight, volume, and failure probability of the entire system [3].The structure of conventional 3SL is shown in Fig. 2(a).The 3SL was first introduced in three-phase dualoutput inverter [4] which is widely known by nine-switch converter (NSC).The NSC is versatile and is used in many different topologies such as, dual-output matrix converter [5], ac-ac converter [6], motor drive [7], [8], dual-output z-source inverter [9], dual-output boost inverter [10], and modular interlinking converter for hybrid ac/dc microgrid [11].Besides NSC, the 3SL are also used in single-phase dual-output inverter as shown in Fig. 2(b) [12], transformerless hybrid power filter [13], multi-input converters [14], dc-dc converter [15], and isolated ac-dc converter [16].
The previous studies signify that the conventional 3SL converters can successfully reduce 25% active switches but they also have limitations such as operating constraints [2] and short-circuit risk [3].Fortunately a good deal of research has already been conducted regarding operation constraints and it has been figured out that the 3SL converters can offer even better efficiency as compared to the conventional counterparts within certain operation ranges [2], [17]- [19].On the other hand, less effort is paid towards the short-circuit risk of 3SL converters and needs further attention.
In both 3SL [see Fig. 2] and 2SL [see Fig. 1(b)] converters, the input voltage source is short-circuited if switches of the same leg are turned on simultaneously.The 2SL converter of Fig. 1(d) has no short-circuit issue because the input is current source.However, it has open-circuit problem if either top ( 1 ,  3 ) or bottom switches ( 2 ,  4 ) are turned off together.The open-circuit issue can be eliminated by using the structures presented in [20], [21], while the short-circuit issue can be resolved by the well-known dual-buck structure patented in [22].Due to the reliable and efficient operation, dual-buck structures are used extensively in various topologies such as dcdc converter [23], full-bridge inverter [24], three-phase inverter [25], split-source inverter [26], differential-boost inverter [27], cascaded full-bridge converters [28], and ac-ac converter [29].It should be noted here that the dual-buck converters in [22]- [29] are based on 2SL converters.Hence keeping in view the benefits of 3SL converters, Bang extended the concept of dualbuck structures to 3SL converters in [3].
The conventional 3SL dual-buck converter [3] is reliable but it has many passive components.To reduce the number of passive components, novel 3SL dual-buck structures are proposed in this article.The motivation and derivation of the proposed structure are analyzed in section II which is followed by switching schemes, mode analysis, and design guidelines in section III, simulation and experimental results in section IV, and comparative analysis in section V.

II. DERIVATION AND MOTIVATION OF THE PROPOSED 3SL
DUAL-BUCK STRUCTURE The current shoot-through problem in conventional 2SL is depicted in Fig. 3.It can be observed that when both switches ( 1 ,  2 ) of the leg are ON due to fault conditions, a low-impedance path is created and the input voltage source is short circuited.The dead-time intervals can reduce the shortcircuit risk but it deteriorates the quality of output voltage waveforms and reduces the achievable voltage gain [30].Besides, the hard switching 2SL converters are normally implemented with IGBTs and cannot avail the benefits of power MOSFETs such as lower switching and conduction losses.This is due to the slow and poor performance of the MOSFETs body diode especially under high voltages [31], [32].The body diodes of silicon carbide (SiC) MOSFETs have exceptionally low reverse-recovery losses [16], [33] and can improve the efficiency of 2SL converters but the short-circuit issue still remains a major reliability concern.
The 2SL dual-buck structure [22] as shown in Fig. 3(b) eliminates the current shoot-through problem and improves the quality of output waveforms as well.Fig. 3(b) shows that inductors appear in the current path even if switches of the same leg are turned on and hence the current shoot-through issue can be avoided.The structure of Fig. 3(b) is reliable but 50% magnetic utilization is the downside of this topology.To improve the power density, a dual-buck structure as shown in Fig. 3(c) is proposed in [24], [28].The key idea of Fig. 3(c) is to use a separate filter inductor and two small-value shootthrough inductors rather than using four bulky inductors similar to Fig. 3(b).
The concept of dual-buck structure is also extended to 3SL dual-output inverters in [3] as shown in Fig. 3(d).Similar to 2SL, the 3SL dual-buck structure has no current shoot-through problem and the quality of output waveforms are improved.[22].(c) 2SL dual-buck inverter proposed in [24], [28].(d) 3SL dual-buck dual-output inverter [3].
Furthermore, as explained in [3], the 3SL dual-buck structure has no reverse recovery issues of the body diodes despite current flowing through them because of the shoot-through inductors appearing in the current path.Besides advantages, it is noteworthy that the conventional 3SL dual-buck structure has large number of passive components.In order to reduce the number of passive components, two novel alternative 3SL dual buck dual-output inverters as shown in Fig. 4 are proposed in this article.The proposed inverters are obtained by replacing only top or bottom two switches of 3SL dual-output inverter [see Fig. 2(b)] with 2SL dual-buck structure of Fig. 3(c).Unlike conventional 3SL dual-buck inverter which requires six external diodes ( 1 −  6 ) and eight shoot-through inductors ( 1 −  8 ), the proposed inverters require only four external diodes ( 1 −  4 ) and two shoot-through inductors ( 1 ,  2 ).Furthermore, the idea of proposed dual-buck structure can be extended to the other 3SL topologies [2], [5]- [8], [10]- [16] as well.As an example, the structures of proposed NSC [2] and multi input converter [14] are shown in Figs. 5 and 6 respectively.Considering that the key idea is same and due to limited number of allowed pages, this article focuses only on the proposed 3SL single-phase dual-buck inverter.

III. SWITCHING STRATEGIES, OPERATION PRINCIPLES AND DESIGN GUIDELINES OF THE PROPOSED SINGLE-PHASE DUAL-
BUCK 3SL INVERTER Like the conventional 3SL converters, the proposed dualoutput inverters of Fig. 4 also share the middle switches of each leg (  2 and  5 ) for both the outputs and hence results in switching constraints.The two output voltages are given by   =     sin(2  ) (1)   =     sin(2   + ).
(2) Where   ,   , and   , are the output voltage, modulation index, and frequency of the top output while   ,   , and   are the output voltage, modulation index and frequency of the bottom output.The phase difference between the two output voltages is represented by  and it varies in the range of 0 ≤  ≤ .The proposed inverters can be either operated in common-frequency (CF) mode when   =   or differentfrequency (DF) mode when   ≠   .Irrespective of the operational modes, switches of the 3SL have only three permissible switching states, which are listed in Table I.The other switching states in which only one switch of the 3SL is ON results in floating the output and are not permissible.The typical modulation for 3SL is depicted in Fig. 7.It can be observed that the top and bottom references generate gate signals for the top and bottom switches ( 1 and  3 ) of the 3SL respectively.The gate signals for the middle switch  2 of the 3SL is obtained by logical XOR operation of  1 and  3 .In order to avoid the forbidden switching states, the top reference should be always greater than or equal to the bottom reference signal.This switching constraint result in doubling the DC-link voltage in worst cases, which can be generally avoided in ac-dc system and CF modes of operation such as online UPS system, constant speed drive, and power conditioner.The continuous and discontinuous pulse-width modulation (PWM) schemes that can be applied to the proposed inverter are briefly analyzed in the following subsections.

A. Continuous PWM scheme
In this PWM scheme, all switches operate at high-frequency.L ft L fb Fig. 5. Proposed dual-buck 3SL NSC.
Where  .and  .are the top and bottom offset voltages used to ensure the switching constraints.For widest range of modulation indices these offset voltages are given by {  .= 0.5 − 0.5   .= 0.5  − 0.5 . ( The illustration of block diagram of Fig. 8 to generate continuous PWM signals for the proposed inverter are shown in Fig. 9.In order to ensure that the top modulating signal   of 3SL is always greater than the bottom modulating signal   , the sum of maximum achievable modulation indices (  +   ) in DF mode must be kept less than or equal to '1'.In contrast to DF mode, the CF mode can achieve higher values of modulation indices and (  +   ) can be equal to '2' given that the phase difference  between the two outputs is zero.To ensure   ≥   , the following inequality which is derived from ( 3)-( 5) by putting   =   =  should be satisfied Using ( 6), the maximum achievable values of   ,   , or  can be determined by assigning values to any two of them.Putting the values of   and , the absolute minimum of right hand side of ( 6) can be calculated which in terms determine the maximum value of   .As an example if   =   = , (6) can be simplified to give the following equation If  = 0  then (7) implies that  ≤ 1 and hence both outputs can achieve modulation indices of '1' which verify the earlier discussion as well.The graph of modulation index  versus phase difference  is shown in Fig. 10.

B. Discontinuous PWM scheme
In discontinuous PWM both top ( 1 ) and bottom ( 3 ) switches of 3SL are clamped and not switching for one half of the output voltage and hence switching losses are reduced.The gate signals generation is illustrated in Fig. 11 and the modulating signals are given by = { 0; 0 ≤ 2   +  ≤    sin(2   +  + );  ≤ 2   +  ≤ 2 (11) In DF mode, the sum of maximum modulation indices (  +   ) is similar to continuous PWM scheme and should be less than or equal to 1.In CF mode, the following equation which is derived from ( 8)-( 11) must be satisfied.
Considering   =   = , (12) can further be simplified as follows By keeping in mind that the value of modulation index  cannot exceed unity, the graph of modulation index  versus phase difference  is plotted and shown in Fig. 10.It can be clearly observed in Fig. 10 that in discontinuous PWM scheme both the outputs can achieve unity modulation indices even when the phase difference  is 60  .The modulation index goes on decreasing when  > 60  but it still remains higher than the continuous PWM scheme.Hence it can be concluded that apart from reducing the losses due to clamping of switches, the discontinuous PWM scheme can also improve the maximum achievable modulation index in CF mode when  > 0  .

C. Operation of the proposed 3SL
The proposed Type I and Type II dual-buck 3SLs which are shown in Fig. 4 consist of a shoot-through inductor ( 1   2 ) and therefore its operation is different from the conventional 3SLs of Figs.2(a) and 3(d).The inductors  1 and  2 actually limit the shoot-through current in fault conditions and provide sufficient time for the protection circuit to shut down the system and hence improve the reliability by protecting the semiconductor devices.The current directions in the proposed 3SL when all the switches are turned ON in the fault conditions are shown in Fig. 12.The shoot-through inductors can be selected based on the following equation Where   =  1 =  2 represent the shoot-through inductors of the switching legs while ∆  ,   , and ∆  represent the increase in current of inductor   , voltage appearing across inductor   , and time duration of the fault conditions respectively.The current directions in the proposed Type I 3SL in normal conditions during each switching states are shown in Figs. 13 to 18.Although there are only three permissible switching states for the 3SL, but different modes can appear for each switching state due to various conditions of output current polarity in the proposed and conventional dual-output inverters [3], [12].As an example, for the switching state 1 in which  1 , and  2 are ON while  3 is off the possible modes are 1, 4, 7, 10, 13, and 16.If the proposed inverter is operated only in CF mode with zero phase shift and unity power factor, then it means that both output voltages and currents are always in phase.As a result, only modes 1 and 4 will appear in the switching state 1.However, if the inverter operates either in CF mode with some phase difference between the two outputs or in DF mode then modes 7, 10, 13, and 16 can appear due to different magnitudes and polarity of the output currents.Apart from this, the inductor  current cannot change instantly and is considered constant during a switching period for simplicity in Figs. 13 to 18.   and   represent the top and bottom output filter inductor currents and are positive if they flow out of the nodes  and  respectively.On the other hand,   and   are considered negative if they flow into the nodes  and  .Furthermore, current through the shoot-through inductor  1 flows in only one direction and is verified through simulations and experimental results in the upcoming section.Now, consider the switching states in the condition when both   and   are greater than zero as shown in Fig. 13.In mode 1 of Fig. 13, the switch  3 is off and the diode  2 is reverse biased.The switch  1 conduct the total output current (  +   ) while the switch  2 and inductor  1 conduct the bottom output current   .The diode  1 conducts only the ripple current of inductor  1 momentarily.In mode 2, the switch  1 conducts the top output current   while the diode  2 and  1 conduct the bottom output current   .The switch  3 conducts only the ripple current of inductor  1 momentarily.In mode 3,  1 carry the current   while the current   flows through  2 ,  2 and  3 ,  1 .The current directions in the remaining possible conditions emerging due to different polarities of   and   are also analyzed similarly and are shown in Figs. 14 to 18.The current flowing in the shoot-through inductor  1 is listed in Table II.The current directions in the proposed type II 3SL are not included due to page limitations.However, simulation results of type II dual-output inverter in the section IV verify the functionality and effectiveness of type II 3SL as well.

D. Design guidelines of the proposed 3SL inverter
The choice of input dc-link voltage   is a very important because the voltage stresses   of input capacitor, switches and diodes are all equal to the input voltage.The input dc-link voltage is inversely proportional to the modulation indices and is determined by the following formula Where   ,   are the magnitudes of the top and bottom outputs voltages while the   and   are the top and bottom modulation indices.In CF mode, each modulation index can reach to unity and hence input dc-link voltage will be equal to the peak value of the output voltages.However as mentioned earlier, the maximum achievable modulation indices (  ,   ) in continuous and discontinuous PWM schemes at commonfrequency (CF) mode depend on the phase difference  between the two output voltages as well.For ease of simplification, consider the range of modulation indices for both the outputs are same which means   =   =  and   =   =   .Putting these values in (a) the normalised voltage stresses in CF mode is given by Using the value of  from ( 7) in ( 16) will give the normalized voltage stresses in CF and continuous PWM scheme    difference between the two outputs is zero and they increase when the phase difference is increased.Furthermore, it can be noticed that the voltage stresses in discontinuous PWM are always less than the continuous PWM scheme and remains at minimum value until the phase difference is increased beyond 60  .In DF mode,   +   ≤ 1 like conventional 3SL inverters.Depending on the modulation indices the top output voltage is either greater, equal, or smaller than the bottom voltage.As an example, if   = .  where 0 ≤  ≤ 1 the top output voltage will be greater than or equal to the bottom output voltage and is represented by   = .  .Putting these values in (15), the normalized voltage stresses to the maximum output voltage (  ) in DF mode can then be calculated as follow Similarly, if   = .  where 0 ≤  ≤ 1 the bottom output voltage will be greater than or equal to the top output voltage and is represented by   = .  .Putting these values in (15), the normalized voltage stresses to the maximum output voltage (  ) in DF mode can then be calculated as follow The graphs of ( ⁄ is a constant which can be greater than or equal to zero, and (  ,   ) is a function whose output is the maximum value between   and   .All the equations are derived in terms of power and voltage of the top load by using   =  1 .  and   =  2 .  where  1 and  2 are constants and they are greater than or equal to zero.As an example, let us   The selection of input capacitors and output filter inductors are similar to the conventional dual-output inverters [3], [12] and the shoot-through inductors can be selected based on (14).The filter inductors are determined by the following general formula Where   is the top or bottom filter inductor,   and  are the corresponding output voltages and duty ratios,   is the switching time period, and ∆  is the allowable inductor current ripple which is usually selected in the range of (20 − 40)% of the corresponding peak load current.In case of motor drive, output filter inductors are not required due to the inductive nature of the motor.

IV. SIMULATION AND EXPERIMENTAL RESULTS
In order to verify the concept of proposed dual-buck 3SL, a hardware prototype of dual-output inverter is built and both simulations and experimental results are provided with system parameters given in Table IV.The picture of hardware prototype is shown in Fig. 22.The inductors   and   are output filter inductors and are not required in case motor drives.Simulation results of proposed type I, type II, and conventional dual-buck dual-output inverter [see Fig. 3(d)] with   = 0.8 and   = 0.58 in CF mode are shown in Fig. 23.Fig. 23(a) shows the top and bottom output voltages (  ,   ), current of top and bottom filter inductors (  ,   ), and shoot-through inductors current ( 1 ,  2 ) of proposed Type I inverter.It can be observed that current through the shoot-through inductors are always unidirectional and the maximum value of  1 is equal to the maximum value of   when both   and   are greater than zero [see light-green highlighted region in Fig. 23].Similarly, the peak value of  1 is equal to the maximum value of   when both   and   are smaller than zero [see lightblue highlighted region].These observations exactly match with the theoretical analysis and Table II     well.Fig. 23(c) shows the simulation waveforms of current flowing through the inductors of the 3SL of conventional dual-buck dual-output inverter of Fig. 3(d) while keeping the equivalent value of shoot-through inductors similar to the proposed 3SL.It should be noticed here that the conventional 3SL dual-buck inverter uses four shoot-through inductors in each switching leg and the peak current of two of them ( 2  ,  4  ) are similar to the inductor current of the proposed inverter (  1   2 ).The current of other two inductors ( 1  ,  3  ) have a high peak value that equals the sum of filter inductors current   +   .
The experimental results are performed with specification mentioned in Table IV and a digital signal controller TMS320F28335 is used to generate gate signals with a constant 0.2 dead-time.Fig. 24 shows the experimental waveforms using continuous PWM scheme in CF mode, phase difference  = 0,   = 0.8, and   = 0.58.Fig. 24(a) shows the output voltages (  ,   ) and output currents (  ,   ) while Fig. 24(b) shows the current of filter inductors (  ,   ) and shoot-through inductors ( 1 ,  2 ).Fig. 25 shows the output voltages (  ,   ) and output currents (  ,   ) in the worst conditions of Table IV that is   = 440  and   = 0.5 .The experimental results with phase difference  = 15  is shown in Fig. 26.The waveforms imply that the switches ( 1 ,  2 , and  3 ) of 3SL operate at high-frequency due to continuous PWM scheme and their peak drain-to-source voltages ( 1 ,  2 , and  3 ) are equal to the input voltage.Experimental results in CF mode and discontinuous PWM scheme are shown in Fig. 27.It can be observed that switches  1 and  3 operate at high frequency in only one half of the output voltage and hence switching losses are reduced.The experimental waveforms at input voltage   equal to 300  and   =   = 1 with phase difference  = 30  while using discontinuous PWM are shown in Fig. 28.The results in Fig. 28 actually confirms the previous analysis that discontinuous PWM can improve range of modulation indices and in terms reduce the voltage stresses on the switches when the phase difference between the two outputs is greater than zero degree.In order to achieve the same  peak output voltages of 300  while using continuous PWM scheme, the achievable modulation indices with  = 30  is reduced to 0.79 according to (7) and Fig. 10.It implies that the required input voltage will be equal to 380  in continuous PWM scheme and hence results in increasing the voltage stresses on the switches.The experimental waveforms of output voltages, current through the shoot-through inductors, filter inductors current, and output currents at   = 400  and   =   = 0.4 in DF mode are shown in Fig. 29.30 shows the output voltages (  ,   ) and output currents (  ,   ) in the worst conditions of Table IV that is   = 440  and   = 0.5 .Finally, two sets of experiments are performed in CF and DF modes in such a way that the top output is connected to a 50 Ω resistive load and the bottom output is connected to a non-linear load.The non-linear load consists of a diode bridge rectifier followed by a 560  capacitor and 100 Ω load resistor.The waveforms of output voltages and currents in CF mode are shown in Fig. 31(a) while in DF mode are shown in Fig. 31(b).These results confirm that the two outputs of the proposed inverter can work independently.

V. COMPARATIVE ANALYSIS OF THE PROPOSED INVERTER
The comparison of the main features of the proposed inverter with the conventional dual-output six-switch inverter (6SWI) [12], conventional dual-buck six-switch inverter (DB-6SWI) [3], and two parallel conventional full-bridge inverters (2FBI) are included in Table V.It can be observed that conventional 6SWI and 2FBI do not need external diodes and shoot-through inductors.However, the current shoot-through issue is a major    reliability concerns for these inverters.Moreover, the quality of output waveforms is deteriorated due to the finite dead-time in the switching signals and the efficiency is low due to the slow MOSFETs body diode.For efficiency comparison of the conventional DB-6SWI with 6SWI, kindly refer to [3].
To elucidate the effectiveness of the proposed inverter during shoot-through fault, the simulations of the proposed [see Fig. 4(a)] and the conventional 6SWI [see Fig. 2(b)] are performed as an example.The simulation results are adequate because we can easily measure the switches current.To test the performance of the conventional and proposed inverters during fault conditions, all the switches of leg 1 ( 1 ,  2 ,   3 ) are turned ON for 1  deliberately.The simulation results of the conventional dual-output inverter are shown in Fig. 32.In Fig. 32,   and   are the top and bottom output voltages  2 is the current flowing through the switch  2 , while the fault signal represents the conditions in which all the switches of leg I are turned ON.It can be observed in Fig. 32 that the input voltage source is during fault conditions and huge current spikes (31000 ) are generated through the switch  2 .These current spikes are also generated in other switches of the Leg 1 ( 1 ,  3 ) and can destroy them.This short-circuit is the main reliability killer in the conventional inverters.The simulation results of the proposed dual-output inverter are shown in Fig. 33.It can be observed that the proposed inverter works well and no dangerous current spikes are generated during fault conditions.This is because the shootthrough inductor  1 protect the sudden short circuit of the input voltage source.
Similarly, Table V shows that the conventional and proposed dual buck inverter have similar performance, but the proposed inverter have a smaller number of passive components and require only 2 inductors and 4 diodes.The current stresses of the shoot-through inductors in the proposed inverter are smaller as compared to the conventional DB-6SWI and can be verified from simulation results of Fig. 23.The voltage and current stresses of the switches and diodes of the proposed DBI which are shown in (15) and Table III are equal to the conventional DB-6SWI [3].However, the conventional DB-6SWI requires two extra diodes and that is why its total peak switching device power   are higher than the proposed inverter.The   indicates the price of semiconductor devices and can be calculated using the method adapted in [34], [35].
For efficiency plot of the proposed inverter, experiments are performed with the same parameters as listed in Table IV except the input voltage is changed to 320 V.The modulation index is varied and the measured efficiency in CF and DF modes are plotted in Fig. 34.Obviously the discontinuous PWM scheme has the highest efficiency because of the reduced switching losses due to clamping action of the switches.The DF mode of operation has slightly higher efficiency because of the reduced conduction losses as compared to the CF mode but the maximum modulation index is limited to 0.5.Apart from this, the conventional DB-6SWI is also built using same semiconductor devices and its efficiency is compared with the proposed inverter in Fig. 35.It can be observed that efficiency of the proposed inverter is slightly higher than the conventional DB-6SWI probably due to reduced magnetic losses of the shoot-through inductors.To get idea about the profile of efficiency variation with respect to output power, the efficiency at different values of input voltage in CF and continuous PWM scheme is shown in Fig. 36.
Finally, THD curves of the proposed inverter with varying modulation index and constant input voltage of 320  in CF mode are included in Fig. 37. Fig. 37 shows that when the deadtime is 0.2  the THD is better as compared to 1  dead-time.This verifies that the proposed dual-buck inverter can achieve better quality of output waveforms due to the reduction in deadtime between the gating signals.

VI. CONCLUSION
In this article a new dual-buck 3SL is proposed for 3SL converters and is successfully introduced in single-phase dualoutput inverter.The proposed inverter has less number of passive components as compared to the conventional dual-buck structure and has no shoot-through concerns with improved quality of output waveforms due to the reduction of dead-time.Detailed theoretical analysis, simulations and experiments are performed and it has been revealed that discontinuous PWM scheme can improve the dc-link voltage utilization in CF mode of operation and hence reduce the switching losses.

Fig. 9 .
Gate signals for the 3SL of proposed inverter using continuous PWM scheme.(a) CF mode.(b) DF mode.

Fig. 10 .Fig. 11 .
Fig. 10.Modulation index versus phase difference in CF mode with both continuous and discontinuous PWM schemes.

.
value of  from(13) in(16) will give the normalized voltage stresses in CF and discontinuous PWM scheme ( The graph of  in continuous and discontinuous PWM scheme with respect  is already included in Fig.10while the graphs of ( equal to the inverse of  are shown in Fig.
values of '' are shown in Fig.20.It can be observed that when  = 0, either   or   is equal to 1 and the normalized voltage stresses are minimum.As the value of  is increased the voltage stresses are also increased.It means that the DF mode of the proposed inverter are suitable for applications in which the modulation index of one of the outputs is closed to zero and the modulation index of the other output is closed to one such as power decoupling of the double line-frequency ripple in single-phase inverters.Apart from voltage stresses, the current stresses are also important for the selection of switches and diodes.The equations for current stresses of semiconductor devices are calculated in the worst-case conditions and are included in TableIII.The current stresses of switches ( 1 ,  3 ,  4 ,  6 ) and diodes ( 1 ,  3 ) are represented by  −1 while the current stresses of switches ( 2 ,  5 ) and diodes ( 2 ,  4 ) are represented by  −2 .  and   are the magnitudes of the current flowing through the top and bottom output loads,   is the output power of the top load,   is the peak value of top output voltage,  1  2

Fig. 19 .Fig. 20 .
Fig. 19.Normalized voltage stresses versus phase difference in CF mode with both continuous and discontinuous PWM schemes.
presented earlier.Fig. 23(b) shows the simulation results of shoot-through inductors current of the Type II inverter at the same output voltages.The similar waveforms of the type I and type II inverters verify the functionality of the proposed type II 3SL as

Fig. 25 .Fig. 26 .
Fig. 25.Experimental waveforms of top output voltage   , bottom output voltage   , top output current   , and bottom output current   in CF mode at   = 440  and   = 0.5 .

29 .Fig. 30 .
Fig. 30.Experimental waveforms of top output voltage   , bottom output voltage   , top output current   , and bottom output current   in DF mode at   = 440  and   = 0.5 .
19.The graph shows that voltage stresses are minimum when the phase State 1 [ 1 and  2 ON,  3 OFF] State 2 [ 1 and  3 ON,  2 OFF] State 3 [ 2 and  3 ON,  1 OFF]Fig.16.Current directions in the proposed type I 3SL during the condition when   > 0;   < 0 and   +   < 0.Fig.17.Current directions in the proposed type I 3SL during the condition when   < 0;   > 0 and   +   > 0.